Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and more specifically, to various methods for a hybrid oxide process for high voltage input/output (I/O) portions of a FinFET device.
Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC' s (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element.
FIG. 1 illustrates a stylized cross-sectional depiction of a state-of-the-art finFET device. A finFET device 100 illustrated in FIG. 1 comprises a plurality of “fins” 110. The source and drain of the finFET are placed horizontally along the fin. A high-k metal gate 120 wraps over the fin, covering it on three sides. The gate 120 defines the length of the finFET device. As dimensions in finFET devices become smaller, performing state-of-the-art gate cut processes subsequent to forming trench silicide contact features may result in residue on the edges of the gate cut regions, which may result in device operations problems.
In many cases, device fabricators establish processing flows that are efficient for producing low voltage, high-performance finFET devices. However, in some cases, it may be desirable to manufacture high-voltage devices. In order to accommodate this desire, designers have implemented alterations to normal manufacturing processes. However, manufacturing devices that are of higher voltage compared to standard voltages generally require implementation of various processes modifications that may cause additional process, integration complexities, and increased costs. For example, certain dielectric layers may be formed thicker than normal in order to accommodate higher than normal operating voltages. This can result in a requirement to modify fin profiles and overall dimensions of the device being manufactured.
In order to accommodate higher than normal voltage operations, designers have implemented thicker dielectric layers in a finFET device, which may have undesirable consequences, such as parasitic capacitances, leakage currents, device size issues, etc. Further, manufacturing devices that have both, a high voltage (HV) region and a low voltage (LV) region call for varied processing steps that require significant process alterations that may be costly and inefficient.
The present disclosure may address and/or at least reduce one or more of the problems identified above.